Exynos5: ddr3: Choose between single or double channel config

Add a 4G configuration and choose it based on the number of banks
declared in config file. A board with 4 SDRAM banks declared (as
per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.

Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>

diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 4d73b4543575a0ab6ae84308e8b45f064e47229f..7c0b12ae51addbffee5af54128ddd2f57a539adf 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
                                                        + DMC_OFFSET);
        pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
 
+       if (CONFIG_NR_DRAM_BANKS > 4) {
+               /* Need both controllers. */
+               mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+               mem->chips_per_channel = 2;
+               mem->chips_to_configure = 2;
+       } else {
+               /* 2GB requires a single controller */
+               mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+       }
+
        /* Enable PAUSE for DREX */
        setbits_le32(&clk->pause, ENABLE_BIT);